This invention is related to semiconductor devices and the fabricating method thereof, and in particular, it is related to the structure of metal insulator semiconductor (MIS) device and to fabricating a contact region for an electrode of MIS devices, for improving the packing density of the devices.
In a MIS device, it is important to obtain a good "ohmic contact" of the contact region, in order to attain high reliability of the semiconductor device. As the scale of integration of the semiconductor device increases, the total size and number of contact regions increases. The size of the contact region is related directly to the packing density of the semiconductor device. Therefore, it is essential to provide a structure and fabricating method which decreases the size and number of contact regions to attain a high integration density.
In the MIS integrated circuit (IC) device, the basic configurations of three-terminal field effect transistors (FET) are arranged in a common-source, and common-drain or common-gate connections in order to increase the packing density. In the basic common-source configuration, for example, the source regions of the MIS FETs are connected to a semiconductor substrate region or well region on which each MIS FET is fabricated through a wiring layer, and are kept at the same potential. In many cases, the semiconductor substrate is supplied with a reference voltage.
Generally, in a complementary metal oxide semiconductor (CMOS) IC, substrate contact regions and well contact regions are positioned one by one for each FET, and, each of the contact regions are connected to each electrode of the CMOS FET by metal wiring lines. However, a wiring line for each FET decreases the integration density of IC, and makes it difficult to fabricate.
A structure of a MIS FET fabricated in a conventional MIS IC is shown in FIGS. 1A-1C. FIG. 1A is a plan view of a prior art MIS FET, FIG. 1B is a sectional view along the line A--A in the FIG. 1A and FIG. 1C is a sectional view along the line B--B in the FIG. 1A.
Referring to the figures, the MIS FET has a semiconductor substrate 1. A source region 5 of the opposite conductivity type as the substrate 1, and a contact diffusion region 7 of the same conductivity type as the substrate 1 are formed on the substrate 1. Contact windows 10a, 10b, and 10c for each electrode are formed in insulating layers 8 and 9; wherein insulating layer 9 is phospho-silicate glass (PSG), 10a is a source electrode contact window corresponding to the source region 5, 10b is a drain electrode contact window corresponding to the drain region 6, and 10c is a substrate electrode contact window corresponding to the substrate contact region 7. The electrode contact windows are connected by a wiring layer, the source region 5 being connected to the substrate 1 by a wiring La. The potential of both the source region and the substrate is the same. Reference numeral 2 is a field oxide film, 3 is a gate oxide film, La is a metal wiring line for a reference voltage, Lb is a metal wiring line supplied with a voltage differ from the reference voltage.
In the prior art method for fabricating the MIS FET, it is necessary to provide a certain distant d.sub.A between gate electrode 4 and an n.sup.+ -type contact region 7 in order to provide for the width for p.sup.+ -type source region 5 and the margin for mask alignment. The width W1.sub.1 of the n.sup.+ -type contact region 7 is necessary to have proper positioning margin d.sub.B so that electrode contact window 10c does not extend beyond the n.sup.30 -type contact region 7. Moreover, it is necessary that the electrode contact windows 10a and 10c have proper positioning margins d.sub.C and d.sub.D in order to maintain the separation between them.
According to the prior art, in order to provide such positioning margins (d.sub.B, d.sub.C and d.sub.D) for contact diffusion regions, the size of the contact region must be large. So, the integration density of the MIS IC is decreased.